Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program

In the previous work the problem of nding gate delays to eliminate glitches has been solved by lin ear programs LP requiring an exponentially large number of constraints By introducing two additional variables per gate namely the fastest and the slow est arrival times besides the gate delay we reduce the number of the LP constraints to be linear in circuit size For example the gate c circuit requires constraints as compared to the million con straints needed with the previous method The re duced constraints provably produce the same exact LP solution as obtained by the exponential set of con straints For the rst time we are able to optimize all ISCAS benchmarks For the c circuit when the input to output delay is constrained not to in crease a design with delay bu ers consumes only peak and average power as compared to an unoptimized design As shown in previous work the use of delay bu ers is essential in this case The practicality of the design is demonstrated by imple menting an optimized bit ALU circuit for which the power consumption was obtained by a circuit level simulator